Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith

ABSTRACT

A circuit and method for deriving an adder output bit from adder input bits, a multiplier circuit, a method of multiplying, a microprocessor and digital signal processor (DSP) employing the circuit or the method and a method of selecting weights and thresholds for logic gates. In one embodiment, the circuit includes: (1) first, second and third logic gates that generate intermediate bits based on threshold comparisons of concatenations of ones of the adder input bits and (2) combinatorial logic that generates the adder output bit from the intermediate bits. In one embodiment, the multiplier includes a summer having at least two inputs with corresponding weights, the inputs corresponding to bits of a multiplicand, the weights based on a multiplier, the summer generating a weighted sum of the multiplicand that represents a multiplication of the multiplicand and the multiplier that is a function of the weighted sum.

TECHNICAL FIELD OF THE INVENTION

[0001] The present invention is directed, in general, to adder andmultiplier circuits and, more specifically, to adder and multipliercircuits employing logic gates having discrete, weighted inputs,combinations of the same, methods of performing combinatorial operationswith such logic gates and combinations thereof.

BACKGROUND OF THE INVENTION

[0002] Digital systems are used extensively in computation and dataprocessing, controls, communications and measurement. Digital systemsuse digital signals that may only assume discrete values. Typically,digital systems use binary signals that employ only two values. Sincesuch systems only use two distinct values, errors caused by componentvariations are minimized. As a result, a digital system may be designedsuch that, for a given input, an output thereof is exactly correct andrepeatable. This gives rise to the extreme accuracy for which digitalsystems are well known.

[0003] Analog systems, on the other hand, use analog signals that varycontinuously over a specified range. Analog systems are thusparticularly vulnerable to error, depending on the accuracy of thecomponents used therein. Since digital systems are generally capable ofgreater accuracy and reliability than analog systems, many tasksformerly performed by analog systems are now performed exclusively bydigital systems.

[0004] A digital system, such as a computer, typically includes an inputdevice, an output device, a processor or central processing unit (CPU)and a data storage device (e.g., random access memory or hard disk). ACPU typically contains an arithmetic/logic unit (ALU) that performsarithmetic functions (e.g., add, subtract, multiply and divide) andlogic functions (e.g., AND, OR and NOT). Additionally, a CPU may alsocontain a floating point unit (FPU) that performs floating pointoperations (e.g., add, subtract, multiply and divide).

[0005] One basic building block of digital systems is a logic gate.Conventional logic gates have one output and one or more inputs. Thenumber of inputs is called the “fan-in” of the gate. The state of theoutput is completely determined by the state(s) of the input(s).

[0006] Logical and arithmetic functions are typically performed by anumber of logic gates coupled together to form a multi-layer network.The maximum number of gates cascaded in series between the input and theoutput of such a network is typically referred to as the number oflayers of gates. Designers are concerned with the number of layers in anetwork for several reasons. In some applications, increasing the numberof layers may reduce the required number of gates and gate inputs (i.e.,fan-in), thus reducing the cost (which may be expressed in terms ofintegrated circuit area) of building the network. Of course, cascading alarge number of gates together may result in unacceptable input-outputdelays and data dependency conditions. When the input of a gate isswitched, a finite time elapses before the output of the gate changes.If a large number of gates are cascaded together to form a network, thetime between an input change and a corresponding change in the networkoutput may become excessive, thereby slowing down the operation of thenetwork.

[0007] Arithmetic functions are particularly susceptible to the effectsof cascaded gates. The serial solution for binary addition is given hereas an example. Initially, a first augend bit and a first addend bit areadded together, to produce a first sum bit and a first carry bit. Thefirst carry bit is then added to the second augend and addend bits toproduce the second sum and carry bits. Since the second sum bit isdependent on the value of the first carry bit, the second sum bit cannotbe computed before the first carry bit is computed. While eachinput-output delay is small, the cumulative input-output delay perceivedwhen adding large numbers, due to the propagation of the carry bit, isproportional to the number of bits added, and may be prohibitive.Techniques (e.g., carry look-ahead, conditional sum or prefixcomputation have been developed for reducing the delay to a logarithmicfunction of the number of input bits to be added. The number of Booleangates (e.g., AND, OR or NOT) used by such techniques is in the range offrom 8n to 35n or 2n log(n) to 3n log(n), where n is the number of bitsto be added and the logarithms are base two.

[0008] Increasing processing power is a continuing goal in thedevelopment of microprocessors. Microprocessor designers are generallyfamiliar with three ways to increase the processing power of a CPU. TheCPU's clock frequency may be increased so that the CPU can perform agreater number of operations in a given time period. Microprocessors aredesigned to operate at increasingly high clock frequencies. Forinstance, the 8080 (introduced in 1974 by the Intel Corporation) wasdesigned to operate at about 2 to 3 MHZ. Today, Intel's Pentium II lineof processors are designed to operate with clock frequencies over 300MHZ. While a higher clock frequency generally results in increasedprocessing power, the higher clock frequency also increases powerdissipation, resulting in higher device operating temperatures.Microprocessor designers, therefore, must address these additionalproblems to avoid catastrophic device failures.

[0009] Another way to increase processing power is to increase input andoutput data bus width, thereby allowing the CPU to process a greateramount of code and data. Early microprocessors were packaged using dualin-line packaging (DIP) technology. Increasing the width of the databuses was both expensive and unrealistic, often resulting in extremelylarge device packages. Today, with the use of pin grid array (PGA)packaging, increasing the size of the data buses no longer poses apackaging problem. Of course, a larger number of transistors is requiredto process the additional information conveyed by the wider data buses.

[0010] Yet another way to increase processing power is to change theinternal architecture of the microprocessor to overlap the execution ofinstructions by, for example, superscaling. This method also requiresthe addition of a large number of transistors, since entire processingstages or execution units must be duplicated. Performing a large numberof instructions in parallel may also result in data dependency problems.

[0011] Accordingly, what is needed in the art is new architectures foraddition circuitry, multiplication circuitry and combinations of thesame that increase the processing power of conventional digital systems.

SUMMARY OF THE INVENTION

[0012] To address the above-discussed deficiencies of the prior art, thepresent invention provides a circuit and method for deriving an adderoutput bit (such as a carry out bit, a carry-generate bit or acarry-propagate bit) from adder input bits (such as a carry in bit, (atleast) first and second addend and augend bits, (at least) first andsecond carry-generate bits or (at least) first and secondcarry-propagate bits. The present invention further provides amultiplier circuit, a method of multiplying, a microprocessor anddigital signal processor (DSP) employing the circuit or the method and amethod of generating weights for logic gates.

[0013] In one embodiment, the circuit includes: (1) first, second andthird logic gates that generate intermediate bits based on thresholdcomparisons of concatenations of ones of the adder input bits and (2)combinatorial logic that generates the adder output bit from theintermediate bits. Circuits may be coupled to one another in layers toyield a wider adder. In such configuration, addend and augend bits aretransformed into carry-generate and carry-propagate bits, which areultimately transformed into a carry out bit.

[0014] The present invention introduces novel digital addition andmultiplication circuits that take advantage of multiple discrete logiclevels to perform respective addition and multiplication operationssignificantly faster than prior art adders and multipliers. Of course,the principles of the present invention extend to cover logic gates thatprocess more than two adder input bits concurrently.

[0015] In one embodiment of the present invention, the first logic gategenerates a first intermediate bit based on a comparison between aconcatenation of ones of the adder input bits and zero. In a relatedembodiment of the present invention, the second logic gate generates asecond intermediate bit based on a comparison between a concatenation ofones of the adder input bits and two. In another related embodiment ofthe present invention, the third logic gate generates a thirdintermediate bit based on a comparison between a concatenation of onesof the adder input bits and four.

[0016] The first, second and third logic gates cooperate to provide thecorrect intermediate bits to the combinatorial circuitry based on thevalues of the various adder input bits.

[0017] In one embodiment of the present invention, the combinatoriallogic comprises first, second and third AND gates and first and secondOR gates coupled to outputs thereof. In an embodiment of the inventionto be illustrated and described, the combinatorial logic generates theadder output bit by additionally employing the ones of the adder inputbits.

[0018] In one embodiment of the present invention, each of the first,second and third logic gates includes: (1) a summer, having at least twobinary inputs with corresponding discrete weights, that generates aweighted sum of input binary digits presented at the at least two binaryinputs and (2) a quantizer, coupled to the summer, that generates anoutput binary digit at a binary output thereof that is a function of theweighted sum. In this embodiment, the logic gates employ an internalrepresentation having more than two logic levels to performcombinatorial operations, but nonetheless have purely binary inputs andoutputs. The binary inputs and outputs ensure that the logic gates canbe employed in an otherwise conventional binary digital architecturewithout requiring the architecture to be modified apart from insertionof the logic gates or circuits that employ the logic gates incombination with more conventional gates, e.g., Boolean gates.

[0019] In one embodiment of the present invention, the discrete weightsare integer multiples of a predetermined number. The predeterminednumber may be “1,” allowing the discrete weights to assume integervalues. Of course, the predetermined number may be any suitable number.

[0020] In one embodiment of the present invention, each of the at leasttwo binary inputs includes: (1) a current source capable of producing asubstantially constant electrical current corresponding to a particulardiscrete weight and (2) a switch, coupled to the current source, thatswitches the electrical current as a function of a correspondingparticular input binary digit. The current source may be derived from avoltage source by way of a resistance. The voltage source may beprovided by a power supply that provides power to other logic circuitry(such as other microprocessor circuitry) that may surround, and interactwith, the logic gate. For purposes of the present invention,“substantially constant electrical current” is defined to besufficiently constant such that the accuracy of the logic gate is notadversely affected. The level of precision required of the current is orcan be a function of the range of discrete integer weights employed inthe logic gate.

[0021] In one embodiment of the present invention, the circuit furtherincludes a threshold input that provides a threshold number to thequantizer, the output binary digit being a function of a relationshipbetween the weighted sum and the threshold number. The threshold numberprovides a bias to the quantizer, allowing a threshold between thebinary output states to assume a value other than zero. In an embodimentto be illustrated and described, the discrete weights are advantageouslyselected to minimize (ideally to zero) the threshold number. This hasthe advantage of minimizing the number or size of current sources orsinks and thus potentially reducing the area (and therefore the cost) ofthe logic gate.

[0022] In one embodiment of the present invention, the correspondingdiscrete weights are provided by a selected one of: (1) current sourcesand (2) current sinks. The current sources may be made to correspond topositive discrete weights and the current sinks may be made tocorrespond to negative discrete weights, such that currents are addedand subtracted in the summer to obtain the desired weighted sum. In thisway, the logic gates of the present invention can be adapted to operatewith respect to discrete weights of either positive or negative sign ora combination thereof.

[0023] In one embodiment of the present invention, the minimum integerweights and thresholds determining the threshold gates of arbitraryfan-ins able to compute the group carry-generate bit from multiplecarry-generate and carry-propagate bits are also presented together withthe method of determining them for gates of arbitrary fan-ins (largerthan two).

[0024] In one embodiment of the present invention, the circuit furtherincludes a plurality of other of the circuits coupled together to form amultiplier circuit. Those skilled in the art will readily perceive otherhighly advantageous applications for the logic gates of the presentinvention. The present invention fully encompasses all applications.

[0025] The present invention further provides a multiplier circuit,including a summer having at least two inputs with correspondingweights, the inputs corresponding to bits of a multiplicand, the weightsbased on a multiplier, the summer generating a weighted sum of themultiplicand. The weighted sum represents the result of a multiplicationof the multiplier and the multiplicand and is analog in nature. Adigital equivalent of the weighted sum may be derived by eithersuccessive comparisons with known analog levels (thereby producing asuccession of result bits) or by converting the analog weighted sum to adigital number in an analog-to-digital (A/D) converter. The weights arepreferably created by bit-shifting the multiplier. A bias may also beapplied to the multiplier circuit to accommodate equations of the type:A×B+C; called inner product or multiply accumulate.

[0026] The foregoing has outlined, rather broadly, preferred andalternative features of the present invention so that those skilled inthe art may better understand the detailed description of the inventionthat follows. Additional features of the invention will be describedhereinafter that form the subject of the claims of the invention. Thoseskilled in the art should appreciate that they can readily use thedisclosed conception and specific embodiment as a basis for designing ormodifying other structures for carrying out the same purposes of thepresent invention. Those skilled in the art should also realize thatsuch equivalent constructions do not depart from the spirit and scope ofthe invention in its broadest form.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] For a more complete understanding of the present invention,reference is now made to the following descriptions taken in conjunctionwith the accompanying drawings, in which:

[0028]FIG. 1 illustrates an embodiment of a logic gate constructedaccording to the principles of the present invention;

[0029]FIG. 2 illustrates an embodiment of a carry bit generating circuitconstructed according to the present invention;

[0030]FIGS. 3A, 3B and 3C illustrate schematic representations ofweights and varying threshold values for the logic gate of FIG. 1 withfan-ins of three, five and seven, respectively;

[0031]FIGS. 4A, 4B and 4C illustrate schematic representations ofweights and fixed threshold values for the logic gate of FIG. 1 withfan-ins of three, five and seven, respectively;

[0032]FIG. 5 illustrates an embodiment of a portion of a multipliercircuit constructed according to the present invention;

[0033]FIG. 6 illustrates a microprocessor employing the gate of FIGS. 1,3A, 3B, 3C, 4A, 4B or 4C or the circuits of FIGS. 2 or 5; and

[0034]FIG. 7 illustrates a digital signal processor (DSP) employing thegate of FIGS. 1, 3A, 3B, 3C, 4A, 4B or 4C or the circuits of FIGS. 2 or5.

DETAILED DESCRIPTION

[0035] Referring initially to FIG. 1, illustrated is an embodiment of alogic gate 100 constructed according to the principles of the presentinvention. The logic gate 100 includes a summer 140, having first andsecond binary inputs 110, 120 with corresponding first and seconddiscrete weights 112, 122. The summer 140 generates a weighted sum offirst and second input binary digits at the first and second binaryinputs 110, 120, respectively. The logic gate 100 further includes aquantizer 150, coupled to the summer 140. The quantizer 150 generates anoutput binary digit at a binary output 130 thereof that is a function ofthe weighted sum.

[0036] In the illustrated embodiment, the logic gate 100 still furtherincludes a threshold input 160 that provides a threshold number to thequantizer 150, which is subtracted from the weighted sum. The outputbinary digit is, therefore, a function of a relationship between theweighted sum and the threshold number. The logic gate 100 may thus bereconfigured to provide different logic functions by changing the valuesof the first and second discrete weights 112, 122, the value of thethreshold input 160 or both.

[0037] In the illustrated embodiment, the first and second binary inputs110, 120 contain first and second current sources 114, 124,respectively. The first and second binary inputs 110, 120 furthercontain first and second switches 116, 126, respectively, coupled to thefirst and second current sources 114, 124. The first and second currentsources 114, 124 produce substantially constant first and secondelectrical currents, respectively, corresponding to the first and seconddiscrete weights 112, 122. The first and second switches 116, 126 thenswitch the first and second electrical currents as a function of thefirst and second input binary digits 110, 120, respectively.

[0038] In the illustrated embodiment, with the first and second discreteweights 112, 122 set at a current corresponding to the number “1” andthe threshold number 160 set at a current corresponding to the number“0.5,” the logic gate 100 functions as a conventional OR gate.

[0039] The logic gate 100 operates as follows. If the first and secondinput binary digits are both zero, the first and second switches 116,126 are off and a current in the summer 140 is substantially zero. Sincethe threshold number is set at “0.5,” the quantizer 150 provides a zeroto the binary output 130. If, however, either the first or second inputbinary digit is one, one of the first or second switches 116, 126 turnson, providing the summer 140 with a current substantially correspondingto the number “1.” Since the one unit of current is greater than thethreshold of “0.5,” the quantizer 150 provides a one to the binaryoutput 130. If both the first and second input binary digits are one,then both the first and second switches 116, 126 turn on, providing thesummer 140 with a current substantially corresponding to the number “2.”In this case, the quantizer 150 also provide a one to the binary output130, the logic gate 100 thus functioning as an OR gate.

[0040] Of course, the threshold number may be modified as required bychanging the threshold input. For example, the threshold number may beset at “1.5” to enable the logic gate 100 to perform an AND function.The quantizer 150 then provides a one to the binary output 130 only whena current corresponding to more than “1.5” appears at the summer 140.

[0041] Turning now to FIG. 2, illustrated is an embodiment of a carrybit generating circuit, generally designated 200, constructed accordingto the present invention. The carry bit generating circuit 200 may beemployed as part of a half or full adder and takes advantage of thelogic gates of the type illustrated in FIG. 1 and is illustrated as onetype of a circuit for generating an adder output bit from adder inputbits.

[0042] The carry bit generating circuit 200 derives a carry out bit (onetype of adder output bit) from a carry in bit and first and secondaddend and augend bits (types of adder input bits). If the carry bitgenerating circuit 200 is employed as part of a larger logic circuit(such as may occur in a multiplier circuit), the addend or augend bitsmay represent sums generated by logic circuits located upstream of thecarry bit generating circuit 200.

[0043] The illustrated embodiment of the carry bit generating circuit200 includes a first logic gate 210 that generates a first intermediatebit based on a comparison between a concatenation of the second addendand augend bits a₂, b₂ and zero. In other words, the second addend andaugend bits a₂, b₂ are concatenated into a string. For the sake ofsimplicity, the second addend and augend bits a₂, b₂ are illustrated asbeing provided as a single input to the first logic gate 210. Inpractice, the second addend and augend bits a₂, b₂ are provided atseparate inputs (as is illustrated with respect to the logic gate 100 ofFIG. 1). The concatenation of the second addend and augend bits a₂, b₂is compared with zero in the first logic gate 210 to determine whetheror not the concatenation exceeds zero. If so, the first logic gate 210generates a one as a first intermediate bit. If not, the first logicgate 210 generates a zero as a first intermediate bit.

[0044] The carry bit generating circuit further includes a second logicgate 220 that generates a second intermediate bit based on a comparisonbetween the concatenation of the second addend and augend bits a₂, b₂and two (as with the logic gate 210, the second addend and augend bitsa₂, b₂ are illustrated as being provided as a single input forsimplicity's sake). In other words, the concatenation that was employedin a comparison with zero in the first logic gate 210 is likewisecompared with two in the second logic gate 220 to determine whether ornot the concatenation exceeds two. If so, the second logic gate 220generates a one as a second intermediate bit. If not, the second logicgate 210 generates a zero as a second intermediate bit.

[0045] The carry bit generating circuit 200 further includes a thirdlogic gate 230 that generates a third intermediate bit based on acomparison between a concatenation of the first addend and augend bitsa₁, b₁ and the carry in bit and four (again, as with the logic gate 210,the second addend and augend bits a₂, b₂ and the carry in bit areillustrated as being provided as a single input for simplicity's sake).In other words, the first addend and augend bits a₁, b₁ and the carry inbit are concatenated into a string. This concatenation is then comparedwith four in the third logic gate 230 to determine whether or not theconcatenation exceeds four. If so, the third logic gate 230 generates aone as a third intermediate bit. If not, the third logic gate 230generates a zero as a third intermediate bit.

[0046] The carry bit generating circuit 200 further includes a first ORgate 240 that generates a fourth intermediate bit from the first addendand augend bits a₁, b₁. If either or both of the first addend and augendbits a₁, b₁ is one, the first OR gate 240 generates a one as a fourthintermediate bit; otherwise, the first OR gate 240 generates a zero as afourth intermediate bit.

[0047] The carry bit generating circuit 200 further includes a first ANDgate 250 that generates a fifth intermediate bit from the first addendand augend bits a₁, b₁. If both of the first addend and augend bits a₁,b₁ are one, the first AND gate 250 generates a one as a fifthintermediate bit; otherwise, the first AND gate 250 generates a zero asa fifth intermediate bit.

[0048] The carry bit generating circuit 200 further includes a secondAND gate 260. The second AND gate 260 is coupled to the first and thirdlogic gates 210, 230 and generates a sixth intermediate bit based on thefirst and third intermediate bits. If the first and third intermediatebits are both one, the second AND gate 260 generates a one as a sixthintermediate bit. Otherwise, the second AND gate 260 generates a zero asa sixth intermediate bit.

[0049] The carry bit generating circuit 200 further includes a third ANDgate 270. The third AND gate 270 is coupled to the second logic gate 220and the first OR gate 240. The third AND gate 270 generates a seventhintermediate bit based on the first intermediate bit and the fourthintermediate bit. If the first intermediate bit and the fourthintermediate bit are one, the third AND gate 270 generates a one as aseventh intermediate bit. Otherwise, the third AND gate 270 generates azero as a seventh intermediate bit.

[0050] Finally, the carry bit generating circuit 200 includes a secondOR gate 280 that is coupled to the second AND gate 260, the third ANDgate 270 and the first AND gate 250. The second OR gate 280 generatesthe carry out bit based on the sixth, seventh and fifth intermediatebits. If any one of the sixth, seventh and fifth intermediate bits isone, the second OR gate 280 generates a one as a carry out bit.Otherwise, the second OR gate 280 generates a zero as a carry out bit.

[0051] Those skilled in the art will note two aspects of the carry bitgenerating circuit 200 of FIG. 2. First, the carry bit generatingcircuit 200 produces a carry out bit that is appropriate to the valuesof the incoming addend, augend and carry in bits. Second, the carry bitgenerating circuit 200 involves only three layers of logic. The uniquearchitecture and characteristics of the first, second and third logicgates 210, 220, 230, not only can possibly accommodate greater numbersof incoming addend and augend bits into larger logic gates withoutincreasing the number of layers of logic, but also can yield a reductionin logic layers over the prior art.

[0052] The following discussion introduces carry-generate andcarry-propagate bits as employed in certain adders. Those skilled in theart will understand such bits. However, for a greater understanding oftheir derivation, see V. Beiu and J. Taylor, On the Circuit Complexityof Sigmoid Feedforward Neural Networks, Neural Networks, Vol. 9, No. 7,1996, which is incorporated herein by reference.

[0053] At this point, it is instructive to set forth a method forobtaining the weights to be employed in a given logic gate, such as thelogic gate 100 of FIG. 1. It has been found that the following Equations(1), (2) and (3) may be employed to choose weights corresponding toincoming carry-generate (v_(Δ/2) for g_(i)) and carry-propagate (w_(Δ/2)for p_(i)) bits, respectively, and threshold values (t_(Δ+2)) for alogic gate having a given fan-in: $\begin{matrix}{v_{\Delta/2} = {1 + {\sum\limits_{i = 0}^{{\Delta/2} - 1}\quad v_{i}} + {\sum\limits_{i = 0}^{{\Delta/2} - 1}\quad w_{i}}}} & (1) \\{w_{\Delta/2} = {{\sum\limits_{i = 0}^{{\Delta/2} - 1}\quad {v_{i}\quad t_{\Delta + 2}}} = {- v_{\Delta/2}}}} & (2) \\{= {{- 1} - {\sum\limits_{i = 0}^{{\Delta/2} - 1}\quad v_{i}} - {\sum\limits_{i = 0}^{{\Delta/2} - 1}\quad w_{i}}}} & (3)\end{matrix}$

[0054] wherein w₀=0, v₀=1, w₁=1 and v₁=2. One of the advantages of theEquations (1), (2) and (3) is that the weights and threshold valuesallow the logic gates to be used in any layer of an adder (thus notrestricting the logic gates to use in only the first layer of the adder,which is a significant limitation of the V. Beiu article cited above andincorporated herein).

[0055] Turning now to FIGS. 3A, 3B and 3C, illustrated are schematicrepresentations of weights and varying threshold values for the logicgate 100 of FIG. 1 with fan-ins of three, five and seven, respectively.The weights (v_(Δ/2) and w_(Δ/2)) and threshold values (t_(Δ+2)) weregenerated in accordance with the Equations (1), (2) and (3) set forthabove, with the initial conditions w₀=0, v₀=1, w₁=1 and v₁=2.

[0056] In FIG. 3A, the gate 100 has three inputs 320, 310, 300,corresponding to carry-generate bit g₁, carry-propagate bit p₁ andcarry-generate bit g₀, respectively. Those skilled in the art willrealize that the weight v₀ associated with the carry-propagate bit p₀always equals 0, so the gate 100 does not need to provide an input forit. The weights corresponding to these inputs 320, 310, 300 are “2,” “1”and “1,” respectively. In addition, the carry bit generating circuit 200is illustrated as having a threshold input 390 having a correspondingweight of “−2.”

[0057] In FIG. 3B, the gate 100 has five inputs 340, 330, 320, 310, 300corresponding to carry-generate bit g₂, carry-propagate bit p₂,carry-generate bit g₁, carry-propagate bit p₁ and carry-generate bit g₀,respectively. The weights corresponding to these inputs 340, 330, 320,310, 300 are “5,” “3,” “2,” “1” and “1,” respectively. In addition, thegate 100 is illustrated as having a threshold input 390 having acorresponding weight of “−5.”

[0058] In FIG. 3C, the gate 100 has seven inputs 360, 350, 340, 330,320, 310, 300 corresponding to carry-generate bit g₃, carry-propagatebit p₃, carry-generate bit g₂, carry-propagate bit p₂, carry-generatebit g₁, carry-propagate bit p₁ and carry-generate bit g₀, respectively.The weights corresponding to these inputs 360, 350, 340, 330, 320, 310,300 are “13,” “8,” “5,” “3,” “2,” “1” and “1,” respectively. Inaddition, the gate 100 is illustrated as having a threshold input 390having a corresponding weight of “−13.”

[0059] Those skilled in the art will perceive an advantage to havingweights and threshold values as small as possible. Accordingly, FIGS.4A, 4B and 4C, illustrate schematic representations of minimal weightsand threshold values for the logic gate 100 of FIG. 1 with fan-ins ofthree, five and seven, respectively. In FIG. 4A, the gate 100 has threeinputs 420, 410, 400, corresponding to carry-generate bit g₁, carrycarry-propagate bit p₁ and carry-generate bit g₀, respectively. Theweights corresponding to these inputs 420, 410, 400 are “2,” “−1” and“1,” respectively. In addition, the gate 100 is illustrated as having athreshold input 490 having a corresponding weight of “−1.”

[0060] In FIG. 4B, the gate 100 has five inputs 440, 430, 420, 410, 400corresponding to carry-generate bit g₂, carry-propagate bit p₂,carry-generate bit g₁, carry-propagate bit p₁ and carry-generate bit g₀,respectively. The weights corresponding to these inputs 440, 430, 420,410, 400 are “5,” “−3,” “2,” “−1” and “1,” respectively. In addition,the gate 100 is illustrated as having a threshold input 490 having acorresponding weight of “−1.”

[0061] In FIG. 4C, the gate 100 has seven inputs 460, 450, 440, 430,420, 410, 400 corresponding to carry-generate bit g₃, carry-propagatebit p₃, carry-generate bit g₂, carry-propagate bit p₂, carry-generatebit g₁, carry-propagate bit p₁ and carry-generate bit g₀, respectively.The weights corresponding to these inputs 460, 450, 440, 430, 420, 410,400 are “13,” “−8,” “5,” “−3,” “2,” “−1” and “1,” respectively. Inaddition, the gate 100 is illustrated as having a threshold input 490having a corresponding weight of “−1.”

[0062] Turning now to FIG. 5, illustrated is an embodiment of a portionof a multiplier circuit, generally designated 500, constructed accordingto the present invention. The multiplier 500 primarily includes a summer510 (symbolized by a “Σ”) and may, in some embodiments, further includea quantizer 520 (a broken line signifies the optionality of thequantizer 520). The summer 510 has at least two inputs 511, 512 (513 . .. 514, 515) that correspond to bits b₀, b₁ (b₂ . . . b_(n−1), b_(n)) ofa multiplier. The multiplier 500 may be of any width or may be packed(advantageously provided with interspersed zeros to separate individualmultipliers packed therein).

[0063] Each of the at least two inputs 511, 512 (513 . . . 514, 515)further has corresponding weights 521, 522 (523 . . . 524, 525). Theweights correspond to bits a₀, a₁, (a₂ . . . a_(n−1), a_(n)) of amultiplicand. As with the multiplier, the multiplicand may be of anywidth or may be packed. As illustrated, the weights 521, 522 (523 . . .524, 525) are bit-shifted versions of the full multiplicand (illustratedin FIG. 5 by appending a progressing number of zeros to the fullmultiplicand).

[0064] From this point, the multiplier circuit 500 functions like thelogic gate 100 of FIG. 1. The weights 521, 522 (523 . . . 524, 525) canbe currents of appropriate magnitude, provided to the summer 510 as afunction of the state of the corresponding at least two inputs 511, 512(513 . . . 514, 515). The summer 510 generates a weighted sum of thebits b₀, b₁, b₂ . . . b_(n−1), b_(n) (which amounts to multiple additionof the bits b₀, b₁, b₂ . . . b_(n−1), b_(n) with the bits a₀, a₁, a₂ . .. a_(n−1), a_(n)) and provides an analog signal that has a current valueequaling the weighted sum. If the weights are embodied in currents ofgiven magnitudes, the summer 510 generates a current having a magnitudesubstantially equal to the weighted sum of the bits b₀, b₁, b₂ . . .b_(n−1), b_(n). As previously described, a digital equivalent of thecurrent (the weighted sum) may be derived by either successivecomparisons with known analog levels, perhaps provided by way of anonlinear function incorporated into the quantizer 520 (therebyproducing a corresponding succession of result bits) or by convertingthe analog weighted sum to a digital number in an A/D converter (notshown).

[0065] The quantizer 520 (which preferably embodies a nonlinearfunction) receives the weighted sum and provides a signal representingone bit of the result of a multiplication of the multiplicand and themultiplier.

[0066]FIG. 5 further illustrates a further input 516 that allows a bias526 to be provided to the multiplication. The bias 526 permits themultiplier circuit 500 to calculate functions of the type A×B+C, where Cis the bias. To activate the bias 526, a one is applied at the furtherinput 516, as shown.

[0067] Turning now to FIG. 6, illustrated is a microprocessor 600employing the gates of FIGS. 1, 3A, 3B, 3C, 4A, 4B or 4C (or gates oflarger fan-in) or the circuits of FIGS. 2 or 5. The microprocessor 600is illustrated as comprising a cache memory 610 for containing data,instructions or a combination thereof. An execution core 620 interactswith the cache memory 610 to draw data or instructions therefrom and toexecute the instructions with respect to the data. The execution core620 comprises an arithmetic and logic unit (ALU) 630 that actuallymanipulates the data in accordance with the instructions. The ALU 630may be pipelined and may be superscalar, allowing instructions to beexecuted faster or in parallel, as may be advantageous in someapplications. Of course, such need not be the case.

[0068] The ALU includes either or both of an adder 631 or a multiplier632 designed to add or multiply incoming data. Both the adder 631 andthe multiplier 632 contain one or more logic gates 100 as illustrated inFIGS. 1, 3A, 3B, 3C, 4A, 4B, 4C or one or more circuits 200, 500 asillustrated in FIGS. 2 and 5. Those skilled in the art will readilyunderstand, however, that the logic gate 100 and circuits 200, 500 ofthe present invention may be employed to advantage in other circuitrywithin a microprocessor. Further, the logic gate 100 and circuits 200,500 of the present invention may be employed in other processing unitsthat are not microprocessors.

[0069] Turning now to FIG. 7, illustrated is a digital signal processor(DSP) 700 employing the gate 100 of FIGS. 1, 3A, 3B, 3C, 4A, 4B or 4C(or gates of larger fan-in) or the circuits of FIGS. 2 or 5. A DSP is,in essence, a microprocessor that is optimized to handle data thatstreams in real time (a signal). The signal may be a sound, a video orany other data stream. Accordingly, the DSP 700 is illustrated ascomprising a signal input 710 and a signal output 720. The signal input710 receives either digital data representing a signal or, if equippedwith an analog-to-digital converter, receives analog data representingthe signal. Likewise, the signal input 720 can produce either digitaldata representing a transformed version of the signal or, if equippedwith a digital-to-analog converter, analog data representing thetransformed version of the signal.

[0070] Interposed between the signal input 710 and the signal output 720is a signal transformation unit 730 that transforms the signals passingtherethrough. Transformations carried out in the signal transformationunit often involve addition or multiplication operations (in fact, onecan think of a signal transformation unit as a microprocessor). Thus,the signal transformation unit 730 is provided with at least an adder731 and/or a multiplier 732 designed to add or multiply portions of anincoming signal. Both the adder(s) and multiplier(s) 731 and themultiplier 732 contain one or more logic gates 100 as illustrated inFIGS. 1, 3A, 3B, 3C, 4A, 4B, 4C or one or more circuits 200, 500 asillustrated in FIGS. 2 and 5. Those skilled in the art will readilyunderstand, however, that the logic gate 100 and circuits 200, 500 ofthe present invention may be employed to advantage in other circuitrywithin a DSP. Further, the logic gate 100 and circuits 200, 500 of thepresent invention may be employed in other DSP that are notmicroprocessor-based.

[0071] From the above, it is apparent that the present inventionprovides a circuit and method for deriving an adder output bit fromadder input bits, a multiplier circuit, a method of multiplying and amicroprocessor and DSP employing the circuit or the method. In oneembodiment, the circuit includes: (1) first, second and third logicgates that generate intermediate bits based on threshold comparisons ofconcatenations of ones of the adder input bits and (2) combinatoriallogic that generates the adder output bit from the intermediate bits. Inone embodiment, the multiplier includes a summer having at least twoinputs with corresponding weights, the inputs corresponding to bits of amultiplicand, the weights based on a multiplier, the summer generating aweighted sum of the multiplicand that represents a multiplication of themultiplicand and the multiplier.

[0072] Although the present invention has been described in detail,those skilled in the art should understand that they can make variouschanges, substitutions and alterations herein without departing from thespirit and scope of the invention in its broadest form.

What is claimed is:
 1. A circuit for deriving an adder output bit fromadder input bits, comprising: first, second and third logic gates thatgenerate intermediate bits based on threshold comparisons ofconcatenations of said adder input bits; and combinatorial logic thatgenerates said adder output bit from said intermediate bits.
 2. Thecircuit as recited in claim 1 wherein said adder output bit is selectedfrom the group consisting of: a carry out bit, a carry-generate bit, anda carry-propagate bit.
 3. The circuit as recited in claim 1 wherein saidadder input bits are selected from the group consisting of: a carry inbit, first and second addend and augend bits, first and secondcarry-generate bits, and first and second carry-propagate bits.
 4. Thecircuit as recited in claim 1 wherein said first logic gate generates afirst intermediate bit based on a comparison between a concatenation ofones of said adder input bits and zero.
 5. The circuit as recited inclaim 1 wherein said second logic gate generates a second intermediatebit based on a comparison between a concatenation of ones of said adderinput bits and two.
 6. The circuit as recited in claim 1 wherein saidthird logic gate generates a third intermediate bit based on acomparison between a concatenation of ones of said adder input bits andfour.
 7. The circuit as recited in claim 1 wherein said combinatoriallogic comprises first and second AND gates and an OR gate coupled tooutputs thereof.
 8. The circuit as recited in claim 1 wherein saidcombinatorial logic generates said carry out bit from ones of said adderinput bits.
 9. The circuit as recited in claim 1 wherein each of saidfirst, second and third logic gates comprises: a summer, having at leasttwo binary inputs with corresponding discrete weights, that generates aweighted sum of input binary digits presented at said at least twobinary inputs; and a quantizer, coupled to said summer, that generatesan output binary digit at a binary output thereof that is a function ofsaid weighted sum.
 10. The circuit as recited in claim 9 wherein saiddiscrete weights are integer multiples of a predetermined number. 11.The circuit as recited in claim 9 wherein each of said at least twobinary inputs comprises: a current source capable of producing asubstantially constant electrical current corresponding to a particulardiscrete weight; and a switch, coupled to said current source, thatswitches said electrical current as a function of a correspondingparticular input binary digit.
 12. The circuit as recited in claim 9further comprising a threshold input that provides a threshold number tosaid quantizer, said output binary digit being a function of arelationship between said weighted sum and said threshold number. 13.The circuit as recited in claim 1 further comprising a plurality ofother of said circuits coupled together to form a multiplier circuit.14. A method of deriving an adder output bit from adder input bits,comprising: generating intermediate bits based on threshold comparisonsof concatenations of said adder input bits; and generating said adderoutput bit from said intermediate bits.
 15. The method as recited inclaim 14 wherein said adder output bit is selected from the groupconsisting of: a carry out bit, a carry-generate bit, and acarry-propagate bit.
 16. The method as recited in claim 14 wherein saidadder input bits are selected from the group consisting of: a carry inbit, first and second addend and augend bits, first and secondcarry-generate bits, and first and second carry-propagate bits.
 17. Themethod as recited in claim 14 wherein said generating said intermediatebits comprises generating a first intermediate bit based on a comparisonbetween a concatenation of ones of said adder input bits and zero. 18.The method as recited in claim 14 wherein said generating saidintermediate bits comprises generating a second intermediate bit basedon a comparison between a concatenation of ones of said adder input bitsand two.
 19. The method as recited in claim 14 wherein said generatingsaid intermediate bits comprises generating a third intermediate bitbased on a comparison between a concatenation of ones of said adderinput bits and four.
 20. The method as recited in claim 14 wherein saidgenerating said adder output bit is carried out by first and second ANDgates and an OR gate coupled to outputs thereof.
 21. The method asrecited in claim 14 wherein said generating said adder output bitcomprises generating said adder output bit from ones of said adder inputbits.
 22. The method as recited in claim 14 wherein said generating saidintermediate bits comprises: generating a weighted sum of input binarydigits presented at said at least two binary inputs; and generating anoutput binary digit at a binary output thereof that is a function ofsaid weighted sum.
 23. The method as recited in claim 22 wherein saiddiscrete weights are integer multiples of a predetermined number. 24.The method as recited in claim 22 wherein each of said at least twobinary inputs comprises: a current source capable of producing asubstantially constant electrical current corresponding to a particulardiscrete weight; and a switch, coupled to said current source, thatswitches said electrical current as a function of a correspondingparticular input binary digit.
 25. The method as recited in claim 22further comprising providing a threshold number, said output binarydigit being a function of a relationship between said weighted sum andsaid threshold number.
 26. A circuit for deriving a carry out bit from acarry in bit and first and second addend and augend bits, comprising: afirst logic gate that generates a first intermediate bit based on acomparison between a concatenation of said second addend and augend bitsand zero; a second logic gate that generates a second intermediate bitbased on a comparison between said concatenation of said second addendand augend bits and two; a third logic gate that generates a thirdintermediate bit based on a comparison between a concatenation of saidfirst addend and augend bits and said carry in bit and four; a first ORgate that generates a fourth intermediate bit based on said first addendand augend bits; a first AND gate that generates a fifth intermediatebit based on said first addend and augend bits; a second AND gate thatgenerates a sixth intermediate bit based on said first and thirdintermediate bits; a third AND gate that generates a seventhintermediate bit based on said second and fourth intermediate bits; anda second OR gate that generates said carry out bit based on said sixth,seventh and fifth intermediate bits.
 27. The circuit as recited in claim26 wherein each of said first, second and third logic gates comprises: asummer, having at least two binary inputs with corresponding discreteweights, that generates a weighted sum of input binary digits presentedat said at least two binary inputs; and a quantizer, coupled to saidsummer, that generates an output binary digit at a binary output thereofthat is a function of said weighted sum.
 28. A multiplier circuit,comprising a summer having at least two inputs with correspondingweights, said inputs corresponding to bits of a multiplicand, saidweights based on a multiplier, said summer generating a weighted sum ofsaid multiplicand that represents a multiplication of said multiplicandand said multiplier.
 29. The multiplier as recited in claim 28 whereinsaid weights are created by bit-shifting said multiplier.
 30. Themultiplier as recited in claim 28 further comprising a further inputthat provides a bias to said quantizer to bias said multiplication. 31.The multiplier as recited in claim 28 wherein said discrete weights areinteger multiples of a predetermined number.
 32. The multiplier asrecited in claim 28 wherein each of said at least two inputs comprises:a current source capable of producing a substantially constantelectrical current corresponding to a particular weight; and a switch,coupled to said current source, that switches said electrical current asa function of a corresponding particular bits of said multiplicand. 33.A method of multiplying a multiplicand by a multiplier, comprisinggenerating a weighted sum of said multiplicand with a summer having atleast two inputs with corresponding weights, said inputs correspondingto bits of said multiplicand, said weights based on a multiplier; andgenerating an output representing a multiplication of said multiplicandand said multiplier that is a function of said weighted sum.
 34. Themethod as recited in claim 33 wherein said generating said weighted sumcomprises bit-shifting said multiplier to create said weights.
 35. Themethod as recited in claim 33 further comprising providing a bias tosaid multiplication.
 36. The method as recited in claim 33 wherein saiddiscrete weights are integer multiples of a predetermined number. 37.The method as recited in claim 33 wherein each of said at least twoinputs comprises: a current source capable of producing a substantiallyconstant electrical current corresponding to a particular weight; and aswitch, coupled to said current source, that switches said electricalcurrent as a function of a corresponding particular bits of saidmultiplicand.
 38. A microprocessor, comprising: a cache memory; and anarithmetic and logic unit containing at least one of an adder and amultiplier, said at least one including a circuit for deriving a carryout bit from a carry in bit and first and second addend and augend bits,including: first, second and third logic gates that generateintermediate bits based on threshold comparisons of concatenations ofsaid carry in bit and said first and second addend and augend bits, andcombinatorial logic that generates said carry out bit from saidintermediate bits.
 39. The microprocessor as recited in claim 38 whereinsaid first logic gate generates a first intermediate bit based on acomparison between a concatenation of said second addend and augend bitsand zero.
 40. The microprocessor as recited in claim 38 wherein saidsecond logic gate generates a second intermediate bit based on acomparison between a concatenation of said second addend and augend bitsand two.
 41. The microprocessor as recited in claim 38 wherein saidthird logic gate generates a third intermediate bit based on acomparison between a concatenation of said first addend and augend bitsand said carry in bit and four.
 42. The microprocessor as recited inclaim 38 wherein said combinatorial logic comprises first, second andthird AND gates and first and second OR gates coupled to outputsthereof.
 43. The microprocessor as recited in claim 38 wherein saidcombinatorial logic generates said carry out bit from said first augendbit and said carry in bit.
 44. The microprocessor as recited in claim 38wherein each of said first, second and third logic gates comprises: asummer, having at least two binary inputs with corresponding discreteweights, that generates a weighted sum of input binary digits presentedat said at least two binary inputs; and a quantizer, coupled to saidsummer, that generates an output binary digit at a binary output thereofthat is a function of said weighted sum.
 45. The microprocessor asrecited in claim 44 wherein said discrete weights are integer multiplesof a predetermined number.
 46. The microprocessor as recited in claim 44wherein each of said at least two binary inputs comprises: a currentsource capable of producing a substantially constant electrical currentcorresponding to a particular discrete weight; and a switch, coupled tosaid current source, that switches said electrical current as a functionof a corresponding particular input binary digit.
 47. The microprocessoras recited in claim 44 wherein said circuit further includes a thresholdinput that provides a threshold number to said quantizer, said outputbinary digit being a function of a relationship between said weightedsum and said threshold number.
 48. The microprocessor as recited inclaim 38 wherein said circuit further includes a plurality of other ofsaid circuits coupled together to form a multiplier circuit.
 49. Adigital signal processor, comprising: a signal input; a signal output;and a signal transformation unit containing at least one of an adder anda multiplier, said at least one including a circuit for deriving a carryout bit from a carry in bit and first and second addend and augend bits,including: first, second and third logic gates that generateintermediate bits based on threshold comparisons of concatenations ofsaid carry in bit and said first and second addend and augend bits, andcombinatorial logic that generates said carry out bit from saidintermediate bits.
 50. The DSP as recited in claim 49 wherein said firstlogic gate generates a first intermediate bit based on a comparisonbetween a concatenation of said second addend and augend bits and zero.51. The DSP as recited in claim 49 wherein said second logic gategenerates a second intermediate bit based on a comparison between aconcatenation of said second addend and augend bits and two.
 52. The DSPas recited in claim 49 wherein said third logic gate generates a thirdintermediate bit based on a comparison between a concatenation of saidfirst addend and augend bits and said carry in bit and four.
 53. The DSPas recited in claim 49 wherein said combinatorial logic comprises first,second and third AND gates and first and second OR gates coupled tooutputs thereof.
 54. The DSP as recited in claim 49 wherein saidcombinatorial logic generates said carry out bit from said first augendbit and said carry in bit.
 55. The DSP as recited in claim 49 whereineach of said first, second and third logic gates comprises: a summer,having at least two binary inputs with corresponding discrete weights,that generates a weighted sum of input binary digits presented at saidat least two binary inputs; and a quantizer, coupled to said summer,that generates an output binary digit at a binary output thereof that isa function of said weighted sum.
 56. The DSP as recited in claim 55wherein said discrete weights are integer multiples of a predeterminednumber.
 57. The DSP as recited in claim 55 wherein each of said at leasttwo binary inputs comprises: a current source capable of producing asubstantially constant electrical current corresponding to a particulardiscrete weight; and a switch, coupled to said current source, thatswitches said electrical current as a function of a correspondingparticular input binary digit.
 58. The DSP as recited in claim 55wherein said circuit further includes a threshold input that provides athreshold number to said quantizer, said output binary digit being afunction of a relationship between said weighted sum and said thresholdnumber.
 59. The DSP as recited in claim 55 wherein said circuit furtherincludes a plurality of other of said circuits coupled together to forma multiplier circuit.
 60. A logic gate, comprising: first, second andthird current paths having preset current magnitudes representingdiscrete weights; first, second and third switches coupled to saidfirst, second and third current paths, respectively, and adapted toreceive binary digits to open or close said first, second and thirdswitches; and a quantizer, coupled to said first, second and thirdswitches, that receives an electrical current that is a function of avalue of said discrete weights and said binary digits, said electricalcurrent representing a result of an operation with respect to saidbinary digits.
 61. The logic gate as recited in claim 60 wherein saidfirst current path is selected from the group consisting of: a currentsource, and a current sink.
 62. The logic gate as recited in claim 60wherein said second current path is selected from the group consistingof: a current source, and a current sink.
 63. The logic gate as recitedin claim 60 wherein said third current path is selected from the groupconsisting of: a current source, and a current sink.
 64. The logic gateas recited in claim 60 wherein said quantizer comprises a thresholdinput that provides a threshold current to the quantizer, said quantizerproducing an output that represents a relationship between saidelectrical current and said threshold current.
 65. A processorcontaining the logic gate as recited in claim 60 .
 66. A DSP containingthe logic gate as recited in claim 60 .
 67. A method of selectingweights and a threshold value for a threshold gate having a given fan-in(Δ), comprising:${{{solvent}\quad v_{\Delta/2}} = {1 + {\sum\limits_{i = 0}^{{\Delta/2} - 1}\quad v_{i}} + {\sum\limits_{i = 0}^{{\Delta/2} - 1}\quad {w_{i}\quad {for}\quad v_{\Delta/2}}}}};$${{{solvent}\quad w_{\Delta/2}} = {\sum\limits_{i = 0}^{{\Delta/2} - 1}{\quad v_{i}\quad {for}\quad w_{\Delta/2}}}};$

solving t_(Δ+2)−σ_(Δ/2) for t_(Δ+2), wherein w₀=0, v₀=1, w₁=1 and v₁=2;and employing said v_(Δ/2) and said w_(Δ/2) as said weights and saidt_(Δ−2) as said threshold value in said threshold gate.
 68. The methodas recited in claim 67 wherein said v_(Δ/2) and said w_(Δ/2) are ofminimum value.
 69. The method as recited in claim 67 wherein saidt_(Δ+2) is of minimum value.